1F3, Atmel ATMega32U4 8-bit microcontroller. Looks like a newer process than the old 2003-vintage AVRs, maybe 250nm instead of 350?
Looks like flash top center, oscillator bottom center, then SRAM and EEPROM in the lower left with analog stuff in the top left.
The logo says Atmel Nantes, so I guess we know which Atmel office did the layout here!
1F4, another Xilinx XC2C32A CPLD. Nothing special about this particular sample.
1F5, Xilinx XC2C32A CPLD polished to a combination of via1, metal 1, and poly.
Not a lot of detail visible without SEM or at least higher magnification in this 180nm device. You can see gates, but not individual transistors in detail.
1F6. Dirty, acid damaged, Xilinx XC2C64A CPLD.
Four 16-macrocell function blocks in a 2x2 grid with global routing down the centerline.
Bitstream flash memory bottom center.
1F7 is another XC2C64A that's MIA, I think I have it on a SEM mount somewhere.
1F8 is an older Xilinx XCR3064XL CoolRunner-XL CPLD. This is made on a 350nm 4-metal process instead of the 180nm used in the CoolRunner-II family.
Xilinx logo from top left corner of sample 1F8, the XCR3064XL
1F9, Xilinx XC95144XL 144-macrocell CPLD. 350nm 4-metal tech.
Looks like there's a bit of defocus here, the die is still on the copper paddle and is slightly off level. Will redo it when I get a tip-tilt stage.
Eight function blocks, four above and four below the central routing spine. Each block contains 18 macrocells.
1F10, Xilinx XCF02 "Platform Flash", cracked during a failed attempt to remove it from the copper paddle many years ago.
Old but still planarized tech, looks to be 350-500 nm with three aluminum interconnect layers.
It's a 2 Mbit JTAG programmable (yes) flash memory which, upon powerup, spits out its contents over an SPI-esque bus protocol into an attached FPGA.
This is what you used in the early 2000s before FPGAs had built-in SPI flash controller logic and could just boot directly from a bog-standard flash memory. Either this or a parallel NOR flash plus a microcontroller.
1G1, Xilinx XC3S50A 50K gate Spartan-3A FPGA, HF etched to substrate with all metal and poly removed. 90nm technology.
Two DCMs (digital PLLs, top center) for clock synthesis.
Three 18x18 bit multipliers (just right of centerline) and three 18 Kbit block RAMs (just right of the multipliers).
Remainder of the fabric area is 1408 LUTs in 352 slices / 176 CLBs, organized as a 16x16 CLB array (256 grid sites, with some holes in the array for the hard IP).
1G2, Xilinx XC3S1000 1M gate Spartan-3 FPGA. Also 90nm technology like the 3A.
Not a whole lot of detail visible on the top metal layer, just power and ground mesh.
1G3, Supereal SR1107.
Here's a hint, if your FTDI FT232R says "Supereal" on the die it's not super real.
Unlike the actual FTDI chips, which are pure RTL state machines (no firmware ROM or data RAM other than the buffer FIFO) this appears to be a bog-standard microcontroller.
1G4, Microchip ENC424J600. This is a 10/100 Mbit successor to the old ENC28J60 SPI-to- 10baseT MAC/PHY chip. Looks like 180nm TSMC at a quick glance although I'm not 100% on that.
Bigger on chip packet buffer, parallel interface for improved throughput (but still supports SPI), and a rather useless by today's standards crypto accelerator. At least unless you want to use MD5, SHA1, or 1024 bit RSA... At least the AES core is still usable but I don't think it supports GCM.
1G5, Macronix MX23L3254 SPI *mask ROM*.
I guess it's meant as a lower cost replacement for SPI flash in high volume applications?
I think this may have come from the Furby but can't recall for sure.
1G6, ADI AD1981B AC97 audio codec.
Mostly analog stuff with what looks like a bit of memory (buffer FIFO?) in the top left corner.
1G7, mask ROM programmed microcontroller from an old RSA SecurID 2fa token.
Very old (1 micron?) 2-metal technology.
1G8, Promise PDC20267 PCI IDE RAID controller. 1999 copyright date on the die.
Looks like they may have been I/O limited on die size? It's hard to tell with the filler metal but it looks like the inner square block has all of the logic. The two big curved traces coming in from the bottom are probably core power and ground, then at the top left is an analog block (likely a dual PLL).
Would need to delayer but I don't think there's anything in the rest of the die. They probably just couldn't fit all of the I/Os needed for several channels of IDE plus PCI into a smaller die area.
1G9, SunPlus SPCA533A digital camera SoC. From one of my 2008-era digital cameras which failed on me after a few years of use.
Some substrate stuck on the underside of the die pushing it off level, so there's alternating areas of good and bad focus. A tilt stage would fix this.
Looks like PLLs in top left and right center, a small memory block (cache?) top left, an even smaller one (FIFO?) top right, then larger memory areas in the bottom right probably containing the main system cache/RAM and maybe some ROM.
Given the multiple small cache-looking memory blocks, this probably has a main CPU plus some accessory DSP core to run compression or something.
1G10, FTDI FT232RL (legit one this time).
Small FIFO SRAM top right, some analog logic (PLL?) bottom right, then just standard cells all over the rest of the die. No CPU.
This is a fairly old technology, something like 500nm, but planarized. It's a huge die for what it does and I'm not surprised that FTDI is NRND'ing it in favor of the newer H series which are made on 180nm UMC.
Ok, that's it for a bit. Time to have dinner and play with the kid until bedtime.
Still have another 30 chips in this tray plus several more partial trays to get through.
Ok, back in the lab for more chip imaging. Let's see how far I can get tonight.
This time I'm testing out the batch mode of the CNC microscope. Here I have scans of six chips running sequentially.
And it's done. 16 mins 30 seconds (990 sec) to take 642 images totaling 731 MB (JPEG), across six chips.
That's an average of 0.648 images per second and 5.9 Mbps of image throughput.
Queued up another 8 chips to run while I stitch and postprocess the first batch.
1H4, Renesas R5H30201 security processor. Used in older iPod accessory authentication.
Not a lot to see, everything is covered in antitamper mesh.
1H5, another Microchip ENC424J600 10/100 Ethernet MAC/PHY.
This one has a bit of debris over the PHY area but has the logo and mask rev markings clearly exposed.
1H6, yet another ENC424J600. This time, partially delayered with HF. Looks like all of the first and a bit of the second metal layer is removed.
You can now clearly see the 24 kB of SRAM buffer just left of the PHY analog block and right of the digital MAC/register interface circuitry.
Aaaand just as I clicked post on that last toot, the scan of eight chips finished.
32 min 55 sec (1975 sec), 1267 images, 1.2 GB.
This averages out to 0.641 images/sec, 4.86 Mbps.
Six more queued up. That's probably going to be it for tonight.
1H7, Silicon Image SiI164 PanelLink Transmitter. TSMC 350nm, immediately recognizable by the coloration.
Has a little doodle of Milhouse in the top left.
@azonenberg everything's coming up Milhouse!
1H10, Linksys LNE100TX PCI 10/100 baseT Ethernet controller.
Has "ADMTek" and "Adhoc Tech" markings on it, so probably an OEM rebrand.
Buffer SRAM bottom right, small memory bottom left, Ethernet PHY analog block top right.
1J1, FTDI FT232H USB-serial/SPI/JTAG bridge.
Die revision A12. Did they seriously need twelve mask spins to get a USB-UART right?
USB PHY top center, buffer SRAM bottom right.
Looks like UMC 180nm from the fill pattern in the bottom right, but also has other fill patterns elsewhere on the die which is weird. MIxed CAD tools and different fill rule decks for each?
