1G10, FTDI FT232RL (legit one this time).
Small FIFO SRAM top right, some analog logic (PLL?) bottom right, then just standard cells all over the rest of the die. No CPU.
This is a fairly old technology, something like 500nm, but planarized. It's a huge die for what it does and I'm not surprised that FTDI is NRND'ing it in favor of the newer H series which are made on 180nm UMC.
Ok, that's it for a bit. Time to have dinner and play with the kid until bedtime.
Still have another 30 chips in this tray plus several more partial trays to get through.
Ok, back in the lab for more chip imaging. Let's see how far I can get tonight.
This time I'm testing out the batch mode of the CNC microscope. Here I have scans of six chips running sequentially.
And it's done. 16 mins 30 seconds (990 sec) to take 642 images totaling 731 MB (JPEG), across six chips.
That's an average of 0.648 images per second and 5.9 Mbps of image throughput.
Queued up another 8 chips to run while I stitch and postprocess the first batch.
1H4, Renesas R5H30201 security processor. Used in older iPod accessory authentication.
Not a lot to see, everything is covered in antitamper mesh.
1H5, another Microchip ENC424J600 10/100 Ethernet MAC/PHY.
This one has a bit of debris over the PHY area but has the logo and mask rev markings clearly exposed.
1H6, yet another ENC424J600. This time, partially delayered with HF. Looks like all of the first and a bit of the second metal layer is removed.
You can now clearly see the 24 kB of SRAM buffer just left of the PHY analog block and right of the digital MAC/register interface circuitry.
Aaaand just as I clicked post on that last toot, the scan of eight chips finished.
32 min 55 sec (1975 sec), 1267 images, 1.2 GB.
This averages out to 0.641 images/sec, 4.86 Mbps.
Six more queued up. That's probably going to be it for tonight.
1H7, Silicon Image SiI164 PanelLink Transmitter. TSMC 350nm, immediately recognizable by the coloration.
Has a little doodle of Milhouse in the top left.
@azonenberg everything's coming up Milhouse!
1H10, Linksys LNE100TX PCI 10/100 baseT Ethernet controller.
Has "ADMTek" and "Adhoc Tech" markings on it, so probably an OEM rebrand.
Buffer SRAM bottom right, small memory bottom left, Ethernet PHY analog block top right.
1J1, FTDI FT232H USB-serial/SPI/JTAG bridge.
Die revision A12. Did they seriously need twelve mask spins to get a USB-UART right?
USB PHY top center, buffer SRAM bottom right.
Looks like UMC 180nm from the fill pattern in the bottom right, but also has other fill patterns elsewhere on the die which is weird. MIxed CAD tools and different fill rule decks for each?
