1H6, yet another ENC424J600. This time, partially delayered with HF. Looks like all of the first and a bit of the second metal layer is removed.
You can now clearly see the 24 kB of SRAM buffer just left of the PHY analog block and right of the digital MAC/register interface circuitry.
Aaaand just as I clicked post on that last toot, the scan of eight chips finished.
32 min 55 sec (1975 sec), 1267 images, 1.2 GB.
This averages out to 0.641 images/sec, 4.86 Mbps.
Six more queued up. That's probably going to be it for tonight.
1H7, Silicon Image SiI164 PanelLink Transmitter. TSMC 350nm, immediately recognizable by the coloration.
Has a little doodle of Milhouse in the top left.
@azonenberg everything's coming up Milhouse!
1H10, Linksys LNE100TX PCI 10/100 baseT Ethernet controller.
Has "ADMTek" and "Adhoc Tech" markings on it, so probably an OEM rebrand.
Buffer SRAM bottom right, small memory bottom left, Ethernet PHY analog block top right.
1J1, FTDI FT232H USB-serial/SPI/JTAG bridge.
Die revision A12. Did they seriously need twelve mask spins to get a USB-UART right?
USB PHY top center, buffer SRAM bottom right.
Looks like UMC 180nm from the fill pattern in the bottom right, but also has other fill patterns elsewhere on the die which is weird. MIxed CAD tools and different fill rule decks for each?
